The present invention relates to a semiconductor design technology, and more particularly, to a semiconductor memory device for generating an output enable signal synchronized with an internal clock signal in response to a read command and Column Address Strobe (CAS) latency information.
In general, a semiconductor memory device, such as Double Data Rate Synchronous DRAM (DDR SDRAM), receives a read command from outside in response to an external clock signal during a read operation and outputs data stored therein to the outside in response to an internal clock signal. That is, in order to output data, the semiconductor memory device uses the internal clock signal, not the external clock signal. This read operation should involve an operation that synchronizes a read command signal synchronized with the external clock signal with the internal clock signal. Like the read command signal, the operation of synchronizing a signal synchronized with a certain clock signal with another clock signal is generally called “domain crossing”.
Such a semiconductor memory device is provided with several circuits for performing a domain crossing operation, one of which is an output enable signal generation circuit. The output enable signal generation circuit domain crosses a read command signal, which is synchronized with an external clock signal and transferred, with an internal clock signal to output a domain crossed signal as an output enable signal. The output enable signal that has been so domain crossed contains CAS latency, and the semiconductor memory device uses the output enable signal to operate in a manner that data is synchronized with the external clock signal and then outputted at a desired time. Here, CAS latency has time information from a time when a read command is applied in one cycle unit of the external clock signal to a time when data is to be outputted.
Meanwhile, the semiconductor memory device is provided with an internal clock signal generation circuit for compensating for skew that may be generated by delay within the semiconductor memory device between the external clock signal and the internal clock signal. One of the representative elements in the internal clock signal generation circuit is a Delay Locked Loop (DLL). A DLL clock signal generated by a DLL will be used herein as an example internal clock signal.
FIG. 1 is a block diagram describing a partial configuration of a conventional semiconductor memory device.
As shown, the conventional semiconductor memory device includes a counter reset signal generator 110, an initialization unit 120, a DLL clock counter 130, an output enable (OE) delay model unit 140, a reset signal synchronizer 150, an external clock counter 160, a count value latch 170, and a count value comparator 180.
The counter reset signal generator 110 synchronizes an output enable reset signal RST_OE with a DLL clock signal CLK_DLL to generate a DLL clock counter reset signal RST_DLL. Here, the output enable reset signal RST_OE is activated by decoding a chip select signal /CS as an external command signal, a row address strobe signal /RAS and a column address strobe signal /CAS, or activated at a completion time of locking operation of a DLL. In general, the counter reset signal generator 110 is composed of a D flip-flop that receives the output enable reset signal RST_OE and outputs it as the DLL clock counter reset signal RST_DLL in response to the DLL clock signal CLK_DLL.
The initialization unit 120 provides the DLL clock counter 130 with an initial count value corresponding to CAS latency CL. That is, the initialization unit 120 sets up the initial count value of the DLL clock counter 130 as output signals INT<0:2> corresponding to the CAS latency CL.
The DLL clock counter 130 is reset in response to the DLL clock counter reset signal RST_DLL and counts the DLL clock signal CLK_DLL from the initial count value corresponding to the output signals INT<0:2> from the initialization unit 120. That is to say, the DLL clock counter 130 generates DLL clock count values CNT_DLL<0:2> that are obtained by counting the DLL clock signal CLK_DLL from the initial count value set up based on the CAS latency CL.
The OE delay model unit 140 models a delay difference value between an external clock signal CLK_EXT used by a domain crossing circuit and the DLL clock signal CLK_DLL to generate an output signal OUT1 by delaying the DLL clock counter reset signal RST_DLL by an asynchronous delay time.
The reset signal synchronizer 150 synchronizes the output signal OUT1 from the OE delay model unit 140 with the external clock signal CLK_EXT to generate an external clock counter reset signal RST_EXT.
The external clock counter 160 is reset in response to the external clock counter reset signal RST_EXT, counts the external clock signal CLK_EXT, and outputs external clock count values CNT_EXT<0:2>. Generally, the external clock counter 160 establishes its initial count value as 0.
The count value latch 170 latches the external clock count values CNT_EXT<0:2> output from the external clock counter 160 in response to a read command RD to output latched external clock count values LAT_CNT<0:2>.
The count value comparator 180 compares the DLL clock count values CNT_DLL<0:2> with the latched external clock count values LAT_CNT<0:2> and activates an output enable signal OE at a time when the two values become the same. Here, the output enable signal OE is synchronized with the DLL clock signal CLK_DLL and contains CAS latency CL information. For reference, the output enable signal OE is used to output plural internal data by adding burst length information thereto thereafter.
Meanwhile, the output enable reset signal RST_OE is generated and provided from a slightly remote part of the above configuration. This allows for occurrence of skew by any variation in process, voltage, and temperature, while the output enable reset signal RST_OE is transferred to the counter reset signal generator 110. This skew of the output enable reset signal RST_OE can cause malfunctioning of the counter reset signal generator 110.
FIG. 2 is a waveform diagram showing an operation waveform when there is occurrence of skew of the output enable reset signal RST_OE shown in FIG. 1. As noted above, the counter reset signal generator 110 is composed of one D flip-flop. In FIG. 2, ‘A’ represents when the counter reset signal generator 110 performs a normal operation and ‘B’ represents when it performs an abnormal operation.
As shown, in case of A, the output enable reset signal RST_OE has a sufficient setup time with respect to a rising edge of the DLL clock signal CLK_DLL. Because of this, the DLL clock counter reset signal RST_DLL is synchronized with the DLL clock signal CLK_DLL and then outputted.
In case of B, the output enable reset signal RST_OE does not have a sufficient setup time with respect to a rising edge of the DLL clock signal CLK_DLL. Because of this, the DLL clock counter reset signal RST_DLL is not synchronized exactly with the DLL clock signal CLK_DLL. In this case, the DLL clock counter reset signal RST_DLL cannot exactly control an operation timing of the DLL clock counter 130 (see FIG. 1). Thus, in order to resolve this problem, the counter reset signal generator 110 has been recently configured as shown in FIG. 3.
FIG. 3 is a detailed block diagram describing the counter reset signal generator 110 shown in FIG. 1.
As shown, the counter reset signal generator 110 includes first and second synchronizers 310 and 330, and first and second latches 350 and 370. Here, each of the first and the second synchronizers 310 and 330 is composed of a D flip-flop, and each of the first and the second latches 350 and 370 is composed of a latch element.
The first synchronizer 310 synchronizes an output enable reset signal RST_OE with a DLL clock signal CLK_DLL to output a first synchronized signal RST_OE1 and the second synchronizer 330 synchronizes the first synchronized signal RST_OE1 with the DLL clock signal CLK_DLL to output a second synchronized signal RST_OE2. The first latch 350 latches the second synchronized signal RST_OE2 in response to the DLL clock signal CLK_DLL to output a latched signal RST_OE25, and the second latch 370 latches the latched signal RST_OE25 to output a DLL clock counter reset signal RST_DLL in response to the DLL clock signal CLK_DLL.
Thus, as in B of FIG. 2, although a setup time problem of the output enable reset signal RST_DLL and the DLL clock signal CLK_DLL occurs in the first synchronizer 310, it is possible for the second synchronizer 330 prepared at a next stage of the first synchronizer 310 to perform a synchronization operation with the DLL clock signal CLK_DLL.
FIG. 4 is a timing diagram describing an operation timing of each signal used for the counter reset signal generator 110 of FIG. 3.
Referring to FIGS. 3 and 4, the first synchronizer 310 synchronizes the activated output enable reset signal RST_OE with a rising edge of the DLL clock signal CLK_DLL to generate the first synchronized signal RST_OE1, and the second synchronizer 330 synchronizes the first synchronized signal RST_OE1 from the first synchronizer 310 with a rising edge of the DLL clock signal CLK_DLL once again to provide the second synchronized signal RST_OE2. The first latch 350 latches the second synchronized signal RST_OE2 from the second synchronizer 330 in response to a falling edge of the DLL clock signal CLK_DLL to output the latched signal RST_OE25, and the second latch 370 latches the latched signal RST_OE25 to output the DLL clock counter reset signal RST_DLL in response to a rising edge of the DLL clock signal CLK_DLL.
As such, the DLL clock counter reset signal RST_DLL is used to determine a counting operation timing of the DLL clock counter 130 shown in FIG. 1. In addition, the DLL clock counter reset signal RST_DLL becomes a source signal of the external clock counter reset signal RST_EXT that determines a counting operation timing of the external clock counter 160 through the OE delay model unit 140 and the reset signal synchronizer 150 in FIG. 1. In other words, the DLL clock counter reset signal RST_DLL acts as a critical factor to determine a counting operation timing of the DLL clock counter 130 and the external clock counter 160.
Meanwhile, the counting operation timing of the DLL clock counter 130 and the external clock counter 160 becomes a critical factor in determining the tRCD (RAS to CAS Delay) as defined in the specification. Here, tRCD defines when a read command is applied after an active operation, and is used as a factor to determine an operating speed of a semiconductor memory device. Typically, the DLL clock counter 130 and the external clock counter 160 have to perform a counting operation after completion of a reset operation before a read command is applied. In other words, if the DLL clock counter 130 and the external clock counter 160 have a delayed reset operation, a read command would be applied with its corresponding delay, thereby degrading tRCD characteristics by the same amount.
In such a configuration as the first and the second synchronizers 310 and 330 and the first and the second latches 350 and 370 in FIG. 3, there is the consumption of 3 tCK on the basis of the DLL clock signal CLK_DLL after the output enable reset signal RST_OE is activated, as in FIG. 4. That is, the DLL clock counter 130 consumes at least 3 tCK to perform a counting operation after reset. Considering the external clock counter 160 that performs a counting operation slower than the DLL clock counter 130, the read command should be applied after more than 3 tCK.
Meanwhile, as semiconductor memory devices are highly integrated, their internal circuits are designed under the design rule of less than submicron level, and as technologies are highly developed, an operating frequency of memory devices, also, increases gradually.
First, such high integration allows chip size of the semiconductor memory device to be decreased gradually, thereby increasing the number of semiconductor memory devices produced on one wafer. These semiconductor memory devices, so produced, undergo a variety of test modes before their mass-production as products. In order to perform such test modes, however, high-price test equipment is required.
Next, in recent circumstances where an operating frequency continues to increase, it is preferable to use test equipment that can support the same frequency so as to test the semiconductor memory devices under optimum environments. However, since such test equipment is very expensive, there is inevitably a burden to purchase test equipments for different operating frequencies. Thus, in the test modes, various tests are carried out by existing test equipment by applying a test clock signal with a lower frequency than an operating frequency in normal mode to the semiconductor memory devices, wherein the test clock signal is supported by the test equipment.
Meanwhile, since the time being consumed in the test modes is related directly to the production cost of the semiconductor memory device, endeavors have been made to reduce the time. For an existing semiconductor memory device, time corresponding to at least 3 tCK is taken to generate the DLL clock counter reset signal RST_DLL. Also, in the test modes, the same situation is present, which means that 3 tCK is very long in the test clock signal of relatively low frequency. That is to say, this causes a prolonged test time by the same amount. The prolonged test time as such increases the production cost, which lowers the competitiveness of producing semiconductor memory devices.